Technical Field
The invention relates to a clock delay technology, and more particularly, relates to a sampling circuit module and a memory control circuit unit applying the sampling circuit module and a data sampling method.
Description of Related Art
In a memory system, a clock signal is often served as a basis for timing sequence in circuit operations. Generally, a clock signal is generated by an oscillator and transmitted to each chip in the memory system through a connecting line. However, a phase shift may occur during the transmission the clock signal. The temperature and change of a voltage provided by the system may also be reasons which cause the phase shift. The phase shift may lead the memory system to a rise in an error rate when performing a data writing or reading operation.
A delay lock loop (DLL) is used to solve an unsynchronization issue of the clock signal transmitted to each chip. The delay lock loop may be mainly classified into two types, analog delay circuits and digital delay circuits. An analog delay circuit controls a delay time of a delay line by using a voltage, and a digital delay circuit dynamically changes a delay amount or a delay stage of the delay line by means of transmitting an instruction signal.
Generally, in order to improve a delay ability of the delay lock loop, it is usually required to increase a number of delay elements in the delay lock loop. However, a circuit area of the delay lock loop may be increased by an excessive number of the delay elements.
Nothing herein should be construed as an admission of knowledge in the prior art of any portion of the present invention. Furthermore, citation or identification of any document in this application is not an admission that such document is available as prior art to the present invention, or that any reference forms a part of the common general knowledge in the art.